1. Field of the Invention
The invention relates in general to IC device substrates alignment and in particular to semiconductor substrates with alignment structures for three dimensional IC fabrication.
2. Brief Discussion of the Related Art
The conventional process to align an IC device substrate is practiced by forming several alignment patterns on the front side of the substrate. Here, a semiconductor wafer W, as shown in FIG. 1a, is used as an example. The semiconductor wafer W comprises a silicon substrate S on its backside WB. An interconnection structure C is formed on the front side WF of the semiconductor wafer W for defining a plurality of IC features. Several alignment patterns M, such as cross patterns, are generally formed on the front side WF for alignment. In some specific fabrication processes, such as metallization or damascene processes, however, the alignment patterns M may be difficult to detect from the backside WB due to obstruction of opaque metallic material in the interconnection structure C. Additional processes for removing a part of the opaque material can be involved thereby improving visibility of the alignment patterns M, however, fabrication costs may potentially increase.
To detect and recognize the alignment patterns M from the backside WB when obstructed by opaque material, as shown in FIG. 1a, a traditional IR imaging apparatus D is applied. The IR imaging apparatus D can capture an image of each alignment pattern M from the backside WB for aligning the wafer W during processes, however, the accuracy and resolution are adversely limited due to IR wavelength substantially longer than 0.75 um. A resolution better than 0.1 um is usually required for the modern semiconductor process, such as the 90 nm technology and beyond.
In three dimensional IC fabrications, such as MEMs and SOI devices, two or more substrates W1 and W2 are bonded and aligned by alignment patterns M as shown in FIG. 1b. The front sides WF1 and WF2 of the substrates W1 and W2 are bonded face to face. Both front sides WF1 and WF2 define a plurality of IC features and comprise alignment patterns M thereon. It may be difficult, however, to detect the alignment patterns M from the backsides WB1 and WB2 of the two substrates W1 and W2 by IR detection during bonding. Hence, conventional wafer alignment is not convenient for three dimensional IC fabrications, and the accuracy can be adversely limited due to IR wavelength when opaque material obstructs the alignment patterns M on the front sides WF1 and WF2 of the substrates W1 and W2.